1. Field of the Invention
The present invention relates generally to semiconductor devices including MOS (Metal Oxide Semiconductor) field effect transistors (hereinafter referred to as "SOI (Silicon-On-Insulator)-MOSFET") formed in a semiconductor layer on an insulation layer and, more particularly, to a semiconductor device in which a degradation in breakdown voltage between sources/drains due to a so-called floating-substrate effect is prevented.
2. Description of the Background Art
Description will now be made on a conventional SOI-MOSFET with reference to FIGS. 1 and 2. Referring to FIGS. 1 and 2, the conventional SOI-MOSFET includes an insulator layer 2 formed on a silicon substrate 1 and a silicon layer 3 formed on insulator layer 2. A channel region 4 having a lower concentration of p type impurities (e.g., 10.sup.16 -10.sup.17 /cm.sup.3) is formed in silicon layer 3. A source region 5 and a drain region 6 having a higher concentration of n type impurities (e.g., 10.sup.19 10.sup.21 /cm.sup.3) are formed on opposite sides of channel region 4 in silicon layer 3.
A transfer gate electrode 8 is formed on channel region 4 with a gate dielectric thin film 7 interposed therebetween. Silicon layer 3 and transfer gate electrode 8 are covered with an interlayer insulation film 9. A contact hole 10 is made in interlayer insulation film 9. A conductive interconnection layer 11 is formed in contact hole 10.
In the SOI-MOSFET thus structured, when a positive voltage is applied to transfer gate electrode 8, n conductivity type carriers (electrons) are induced into an upper layer of p type channel region 4. The upper layer of channel region 4 is inverted to be of the same n conductivity type as that of source and drain regions 5 and 6. This enables a current to flow between source and drain regions 5 and 6. Further, since the concentration of the n type carriers induced into the upper layer of channel region 4 varies dependently on a gate voltage to be applied to transfer gate electrode 8, the amount of the current flowing in channel region 4 can be controlled by the gate voltage. This is an operation principle of the MOSFET.
When silicon layer 3 has a relatively large thickness such as of approximately 5000.ANG., if the SOI-MOSFET is rendered operative by application of a gate voltage, then carriers are accelerated at a high speed in channel region 4. The carriers accelerated in channel region 4 generate pairs of electrons and holes by impact ionization in the vicinity of drain region 6. The generated electrons flow into n.sup.+ drain region 6, while the generated holes are left and stored in channel region 4. This causes an increase in potential of channel region 4 and an increase in channel current, thereby causing an unpreferable so-called kink effect on curves indicating the relationship between a drain voltage and a drain current. The kink effect is described in, for example, IEEE Electron Device Letter Vol. 9, No. 2, pp. 97-99, 1988.
The kink effect will now be explained as follows by use of energy band diagrams shown in FIGS. 3A-3C. The channel region and the source/drain regions on the opposite sides of the channel region form npn junction. An energy band thereof is as shown in FIG. 3A prior to junction of the respective regions. More specifically, a Fermi level E.sub.FN of the n type source and drain regions is higher than a Fermi level E.sub.FP of the p type channel region. If the respective regions are connected together, the energy band thereof is balanced when the respective Fermi levels are equal, so that a potential of the n type source/drain regions becomes higher than that of the p type channel region as shown in FIG. 3B. In this state, when the source region is grounded and a potential of +4V is applied to the drain region, holes are stored in the upper layer of the channel region due to the kink effect, resulting in an increase in potential of the channel region. Accordingly, such an energy band as shown in FIG. 3C is provided. This facilitates the flow of electrons from the source region to the drain region in a direction indicated by the arrow B, thereby causing a degradation in breakdown voltage developed across the source/drain regions.
On the other hand, if silicon layer 3 has a very small thickness such as of approximately 500 to 1500.ANG., an SOI-MOSFET having such silicon layer 3 has the following excellent characteristics as compared with a normal SOI-MOSFET having relatively thick silicon layer 3 causing the above-described kink effect. For example, channel region 4 provided with thin silicon layer 3 is depleted overall by application of a voltage to transfer gate electrode 8, and a potential of channel region 4 is also controlled by the gate electrode. This results in reductions in a punch through phenomenon that a current flowing in channel region 4 cannot be controlled by transfer gate electrode 8 and in a short channel effect that a threshold voltage is abnormally decreased when the transfer gate electrode has a small length.
However, if the overall channel region 4 is completely depleted, then the potential in channel region 4 becomes higher than that provided in the normal MOSFET. Accordingly, an electric barrier provided between source region 5 and channel region 4 is decreased. In addition, if the holes produced by the above-described impact ionization are temporarily stored in channel region 4, then the potential in channel region 4 further rises, whereby electrons are abruptly injected into channel region 4 from source region 5. That is, there is such a disadvantage that the breakdown voltage developed across the source/drain regions is liable to decrease in a thin-film SOI-MOSFET.
A degradation in V.sub.D -I.sub.D characteristic of the MOSFET having relatively thick silicon layer 3 due to the kink effect appears in the form of distortion in circles indicated by the arrow A in the graph of FIG. 4. Further, a degradation in breakdown voltage developed across the source/drain regions in the MOSFET having relatively thin silicon layer 3 appears in the form of such a phenomenon that a drain current I.sub.D abruptly increases if a drain voltage V.sub.D exceeds a predetermined value, as shown in the graph of FIG. 5.